Asic Design Verification Engineer

Description:

• We are partnered up with a global semiconducting organisation who are based in Ireland who are looking for a ASIC Design Verification Engineer to work in their Sensors team onsite.

   

  Relocation Support is available

   

  Responsibilities

• Test plan development based on Design documents and interaction with design/systems engineers
• Verifying sensor algorithms RTL for ASIC tapeout quality delivery
• Developing Testbenches and Verification Components such as UVCs, C models, and Vertical/Horizontal re-usable Verification Environments
• Writing SystemVerilog assertions
• Debugging, verifying, optimizing, and bit-exact matching with test vectors

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  Requirements

• 5+ years ASIC design verification, UVM-based functional verification.
• Gate level Simulation debug and usage of power extraction tools is a plus
• Experienced with Assertions like System Verilog Assertions
• Extensive usage of RTL simulation tools.
• UVM, System Verilog, Perl/Python shell-scripting skills required