Design Methodology Engineer

Description:

Qualcomm’s Design Technology team is seeking a motivated engineer to drive development of advanced signoff methodologies in STA. The engineer should be proficient in static timing analysis using the Synopsys Primetime toolset and should have strong coding skills in scripting languages such as Python and TCL. Domain knowledge including place and route tools and concepts, power analysis and optimization, and IR drop analysis and optimization is also helpful.

The engineer is expected to propose, develop, and validate new methodologies, engage with vendors, CAD, and design teams, and work collaboratively with worldwide teams.
 

• Please note this role will require 5 days per week onsite in our Cork office*
  
   

Roles And Responsibilities
 

• Develop and drive analysis and optimization methodologies for interaction of IR drop and STA
• Develop physical-aware timing and IR drop ECO solutions
• Collaborate closely with physical design and timing teams to drive methodologies to optimize power and minimize hotspots
• Work with CAD and tool vendors to develop and validate new flows and methodologies
• Work on design power profiling and electromigration analysis
• Develop strategies for PDN analysis and signoff for 3DIC, datacenter, and chiplet designs
  
   

Required Skills And Experience
 

• Expertise in static timing analysis . Hands-on experience with Primetime or Tempus
• Strong coding skills in languages such as Python, TCL
• In-depth knowledge of physical design
• Sound conceptual understanding of low power design techniques like voltage/power islands, power gating, clock gating, retention designs etc.
• Strong methodology development background. Ability to drive solutions by creating and implementing algorithms
• Strong analysis and communication skills
  
   

Preferred Skills And Experience
 

• MS/PhD degree in Science, Electrical/Electronics Engineering and 2+ years of industry experience
• Familiarity with PnR tools, FC, Innovus is a plus
• Good insight in designing flows and software structure