Description:
Qualcomm’s Mixed-Signal IP (MSIP) Design Verification team is seeking Mixed-Signal Design Verification Engineers to join our team in Cork, Ireland. The Qualcomm Cork site is home to a range of MSIP teams working on cutting edge designs for the latest Snapdragon SoCs in the latest technology nodes, and the successful candidate will work on mixed-signal verification for several key mixed-signal PHY IPs including DDR, USB, PCIE, eDP, DPRX, HDMI, SGMII, DSI, CSI as well as PLL IP and more.
The Design Verification team in Cork uses the latest tools and verification techniques in leading edge silicon nodes at 3nm and below and team members work directly with architecture, design, software and SoC teams in Ireland and other global Qualcomm locations.
Responsibilities Will Include:
- SV/UVM based Design Verification of SerDes, DDR & PLL Mixed-Signal PHY IP
- Emulation experience is desired along with SV/UVM based simulation.
- Work closely with analog and digital front-end design teams to verify RTL and Analog/Mixed-Signal Designs in next-generation SerDes, DDR & PLL IP
- Interact with architecture, design, physical design, software, test and SoC teams to verify and integrate SerDes, DDR & PLL IP designs into the latest Qualcomm Snapdragon products
Skills And Experience We Would Love To See
- Bachelor's degree in Engineering, Computer Science or related field.
- Experience in design and verification of hardware and software on SoCs and SoC/IP Methodologies for verifying complex units using industry standard tools and technologies
- Knowledge in developing unit and SoC/IP level test benches using UVM.
- Constrained random functional verification environment in System Verilog/UVM with excellent debugging skills.
- Experience in Low power verification using UPF at RTL and GLS simulation level.
- Experience in Power Aware Gate Level Simulation (GLS) verification flow with zero delay and SDF annotated simulation.
- Experience of pre and post-silicon verification testflow and automated test benches. Post silicon ATE/PTE vector bringup and bench characterization support.
- Knowledge of test-plan development, coverage (code/functional) analysis, transaction level modelling, constrained random verification, assertion based and formal verification techniques with System Verilog
- Experience with Verilog, SystemVerilog, Assertions, Python/TCL/Perl/shell-scripting.
- Experience in analog mixed signal verification techniques will be a plus.
- Excellent communication skills
Minimum Qualifications:
- Bachelor's degree in Science, Engineering, or related field.
- 2+ years design verification, or related work experience.