Senior Design Verification Engineer

Description:

We are seeking Senior Digital Design Verification Engineers to work with one of the largest and most well-known semiconductor & graphics companies in the world and work on topics including the development of next-generation industry-leading CPU/GPU processors or sensors.

You will be working alongside members of the architecture, software and SoC teams in Ireland and other global locations.

Responsibilities:

• Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification
• Developing Testbenches and Verification Components such as UVCs, C models, and Vertical/Horizontal re-usable Verification Environments.
• Test plan development based on Design documents and interaction with design/systems engineers
• Implementing C model integration within UVM framework.
• Writing SystemVerilog assertions

Required Skills:

• Bachelor's/Master’s degree in Science, Engineering, etc.
• 3+ years of ASIC design verification, UVM-based functional verification, or related work experience.
• Experienced with Assertions like System Verilog Assertions
• Experience with debugging test failures and reporting verification results to achieve the expected code/functional/line coverage goals
• Extensive usage of RTL simulation tools.
• UVM, System Verilog, Perl/Python shell-scripting skills required