Sta Design Engineer

Description:

As a Qualcomm STA Engineer, you will perform static timing analysis, develop timing constraints, and optimize timing performance for a variety of high-performance, high-quality, low-power world-class products. You will collaborate with cross-functional teams to ensure timing closure and validate timing models, contributing to the successful execution of product development.

The STA team at Qualcomm is responsible for evaluating block-level and top-level timing to ensure optimal performance and power efficiency in advanced cores and SOCs. As a STA Engineer, you will conduct static timing analysis on gate-level PNR netlists, provide feedback to RTL, Synthesis and Physical Design teams to improve PPA, collaborate with cross-functional teams to meet timing constraints, and produce timing ECOs to resolve violations. Your role is crucial in developing high-performance, low-power ASIC solutions that drive the future of technology.
 

• Please note this role will require 5 days per week onsite in our Cork office*
  
   

You Will Be Responsible For

You will be a member of a team working on timing signoff for Snapdragon Cores and SOCs, methodologies and flows:
 

• Performing STA and timing closure for complex cores and full-chip SOCs
• Enhancing techniques and methodologies for STA and timing closure
• Driving accuracy of timing closure and static/dynamic flows to reduce turnaround time
• Ensuring compliance with timing signoff checklists and criteria
• Automation for timing and power data mining and processing
• Participating in project proposal development including key milestones and deliverables
• Executing and delivering project goals in a timely manner with production support
• Resolving issues in all phases of development to ensure smooth project execution
  
   

We Would Love To See
 

• Expertise in STA tools (PrimeTime, PrimeShield or Tempus) used for hierarchical analysis in large SoCs
• Hands-on experience with Tweaker, PrimeClosure, PTECO, or Tempus ECO for timing closure
• Highly proficient in automation: Python, TCL or Perl
• Strong knowledge of ASIC design flows (RTL-to-GDS)
• Interest in Design for Parametric Yield is an added advantage
• Comfortable with extraction, circuit simulation tools and environments is a plus
• Excellent problem-solving skills and result-driven approach, able to work and drive practical solutions under research environment.
• Good communication and personal skills in a multi-disciplinary, fast-paced engineering environment
• 4+ years of related work experience